Thin Film Transistors (TFTs) relate to field effect transistors (FETs), in which an electric field created by the gate controls the flow of current along the transistor channel from the source to the drain. TFTs, including organic thin film transistors and those based on the use of amorphous silicon (a-Si), are being developed for a variety of applications among which are back-plane for non-emissive displays (such as liquid crystal display, electronic ink), emissive displays (such as Organic Light-Emitting Diode (OLED) display), and logic circuits.
The largest obstacle in the road to full realization of the potential is the low charge mobility restricting the flow of carriers across the channel which limits the current such a transistor can provide. For example, a transistor that is much larger than the LED was used in order to supply enough current density to turn the LED emission on [1]. In the logic area, it limits the switching speed (charging gate capacitance takes too long) and enhances the sensitivity to background noise.
High brightness and efficient organic-LED based screens are being developed by industry giants such as Samsung, Philips, Sony, Kodak, and Dupont. Recently, high-quality organic displays made on glass substrates have begun to penetrate the market, and larger screens are expected to appear in the near future. The exciting potential of organic LEDs originates from their flexibility. Companies around the globe are seeking to develop a flexible backplane transistor array that will enable a flexible emissive display. So far, the limited charge-carrier mobility of organic materials (less than 1 cm2v−1s−1) is not sufficient to provide the necessary current to the emitting diode.
The performance of organic TFTs are at best comparable to those based on amorphous silicon, and is still poor compared to inorganic crystalline material based devices. Most efforts are still focused on the traditional lateral TFT structure. These approaches include those aimed at reducing the contacts resistance or the trapping states of the insulator-channel interface; increasing the dielectric constant of the gate dielectrics or reducing the channel length using sophisticated lithography.
In the margins of organic TFT (OTFT) research, two main approaches have been introduced so far:
The first approach is based on the creation of a vertically stacked transistor so that a distance between its electrodes (i.e. channel length) is defined by the thickness of an organic layer that can be as low as 100 nm (compared to several microns in planar architecture) using solution processing technology. Apart from the fabrication price reduction, these devices should have enhanced DC performance and better switching speed.
A gate-source-drain vertical organic field effect transistor (VOFET) structure has been developed [5], in which the gate electrode is placed below the source electrode and is separated from the active region by an insulating (dielectric) layer. This is illustrated in FIGS. 1a-b showing (a) the VOFET structure and schematics of the common source electrode roughness, and (b) the atomic force microscope image of the source electrode surface. This approach relies on making a thin yet generally conducting metallic electrode. The authors define this structure as an active cell on top of a capacitor cell. This transistor utilizes, for the source electrode, a highly non uniform film in that it has thin and thick regions. FIG. 1c shows the VOFET conductance characteristics for different gate-source voltage. The impressive performance of this device includes 10 mA channel current at the drain-source potential YDS of 4V and the gate-source potential VGS of 5V with an ON/OFF ratio close to 4×106. However, this transistor design suffers from the need to produce the source electrode with a finely tuned roughness (i.e., optimization of thin versus thick properties of the film), which lowers reproducibility of these results.
The second approach is based on a standard lateral configuration, but where the channel length is effectively shortened. This can be achieved by including highly conductive regions in the channel. Shortening the effective length that the charge needs to pass through in the semiconductor reduces the overall channel resistance and results in a higher current.
A self-forming one dimensional nanostructure has been developed, being designed as a wave-ordered structure with a controllable period (20-180 nm), which resulted from the off-normal bombardment of amorphous silicon layers by low-energy (about 1-10 keV) nitrogen ions [6]. According to this technique, the nanostructure has been modified by reactive-ion etching in plasma to form a periodic nano-mask on the surface of the channel region of a metal-oxide-semiconductor field effect transistor (MOSFET). Implantation of arsenic ions through the nano-mask followed by the technological steps completing the fabrication of the MOSFET resulted in a periodically doped channel field-effect transistor (PDCFET), which can be considered as a chain of short-channel MOSFETs with a common gate or an effectively single FET with a shorter channel. This is illustrated in FIG. 2a showing schematic description of a nanoperiodic doping profile of the channel region.
Some other techniques of the planar-architecture field utilize creation of a sub-percolation network of conducting carbon-nanotubes between the contacts of the planar structure so as to reduce the effective distance between the contacts [7]. More specifically, conductive carbon nanotubes were employed as a filler, and were spun onto the channel region with the aim of filling it to the point where it is just below percolation threshold. This is illustrated in FIG. 2b, showing schematic description of a channel filled with conductive carbon nanotubes to below percolation threshold. This approach is restricted by the requirement to avoid a short circuit through the conductive nanotubes, which dictates using a relatively low density of tubes. This requirement, in turn, leads to a very limited effect.
Amorphous silicon based TFTs also typically suffer from slow switching speeds and low current handling capacity, because the electronic properties of amorphous silicon fall short of single or poly crystalline silicon. The known solutions for this problem include enhancement of the electronic properties of the material, e.g. replacing amorphous silicon with polysilicon; reduction of feature size to reduce the transistor gate length; and the use of alternative transistor architectures. All these solutions require significant research and changes to existing production lines.